1. Field of the Invention
The present invention relates to a phase error correction circuit for correcting a phase shift in a received signal, and a receiver incorporating such a phase error correction circuit, in the field of wired or wireless communications.
2. Description of the Background Art
In the field of wired or wireless communications, techniques of splitting data in frames for transmission/reception are widely used. In the case of cellular phones, for example, data is split into frames of a predetermined length, with a preamble, a unique word, or the like being added in front of each frame. A preamble is provided at the beginning of each frame. A receiver, while receiving a preamble, performs processes such as gain control, symbol clock reproduction, or phase shift detection, in order to control the manner in which subsequent portions to a preamble (e.g., a unique word and/or data) are received.
A phase shift may occur between a signal transmitted from a transmitter and the signal received by a receiver, due to a frequency offset between local oscillators used in both devices, phase noise, or the like. Therefore, a receiver is equipped with a phase error correction circuit for correcting a phase shift in the received signal. The receiver regards the phase shift which has been detected while receiving a preamble as a phase correction value for portions subsequent to the preamble, and performs a phase correction for the portions subsequent to the preamble by using this value. When calculating a correction value using this method, however, a demodulation error may be induced if the correction value is calculated not only with respect to the phase shift in the preamble but also portions other than the preamble. Therefore, the calculation of the correction value must be based only on the phase shift in the preamble.
FIG. 40 is a block diagram illustrating the structure of a conventional demodulator described in Japanese Patent No. 2643792. The demodulator shown in FIG. 40 detects a preamble which is contained in the received signal, and infers a carrier frequency error based on the preamble detection signal. An input signal 4020 to this demodulator is a π/4 shift DQPSK (Differential Quadrature Phase Shift Keying) modulated signal containing a preamble of a certain pattern.
In FIG. 40, a delay detection means 4001 detects an input signal 4020 which is a π/4 shift DQPSK modulated signal. An averaging circuit 4002 subjects the detected signal to an averaging with respect to each of its two orthogonal signal components, and outputs a phase vector 4021. A preamble detection means 4003 includes a power detection circuit 4004, which calculates the magnitude of the phase vector 4021, and a comparison circuit 4005, which compares the calculated magnitude against a predetermined threshold level. The comparison circuit 4005 outputs a preamble detection signal 4022 if the magnitude of the phase vector 4021 exceeds a predetermined threshold level. A phase angle calculation means 4006 includes a flip-flop 4007, which fetches and retains the phase vector 4021 at the time when the preamble detection signal 4022 is output, and an arc tangent conversion ROM 4008, which outputs the phase angle of the retained phase vector. An adder 4009 adds π/2 to the calculated phase angle. Based on an output signal from the adder 4009, a frequency error calculation means 4010 calculates a carrier frequency error. An oscillation frequency of a variable frequency oscillation means 4011 is controlled based on the carrier frequency error calculated by the frequency error calculation means 4010. Using the oscillation signal output from the variable frequency oscillation means 4011, a frequency converter 4012 subjects the input signal 4020 to a frequency conversion. As a result, the frequency error of the input signal 4020 is corrected. A recovery circuit 4013 recovers the carrier and a clock from the input signal which has been subjected to frequency error correction, and outputs a demodulated signal 4023 through synchronization detection.
Thus, in order to obtain a carrier frequency error while receiving a preamble, the above-described conventional phase error correction circuit detects a preamble by comparing the magnitude of the phase vector 4021 against a predetermined threshold level, and then calculates a frequency error correction value based on the preamble detection signal 4022.
When a frame-formatted signal is sent through burst transmission, the receiver, which wants to detect the transmitted preamble, performs such a gain control that the gain for the received signal is initially made maximum. As a result, the amplitude of the detected signal is saturated in a earlier portion of the preamble. Thereafter, the amplitude of the detected signal is reduced over time through the gain control, until the gain control becomes stabilized in a later portion of the preamble. Therefore, the calculation of a correction value while receiving a preamble should really be made by calculating the correction value at the later portion of the preamble, where gain control has been stabilized.
However, in accordance with the above conventional phase error correction circuit, the magnitude of the phase vector varies depending on the state of reception. This makes it difficult to identify a later portion of the preamble based on a comparison of the magnitude of the phase vector against a predetermined threshold level. The conventional phase error correction circuit also has problems associated with temporal variations in amplitude due to fading, and gain control stability.